Electronic devices including mobile and portable devices such as cell phones, personal digital assistants (PDA), digital cameras, and combinations thereof, require static random access memory (SRAM) chips with low standby power and low operating power consumption. An SRAM chip may comprise millions of SRAM cells similar to the 6T SRAM cell 100 shown in FIG. 1a. Other types of SRAM cells include four transistor (4T) SRAM cells and single transistor (1T) SRAM cells, for example. Shallow trench isolation (STI) structures are commonly used to define the active areas of and to electrically isolate SRAM cells.
However, undesired recesses known as divots may form directly adjacent transistor active areas in shallow trench isolation structures during the STI manufacturing process. The conventional STI process flow includes pad oxide and silicon nitride (SiN) deposition, active area masking, nitride/oxide etching, silicon (Si) trench etching, liner oxidation, chemical vapor deposition (CVD) oxide filling, chemical mechanical polishing (CMP), and nitride and pad oxide removal. Well known issues in conventional STI processes include divot formation (i.e., oxide recess, or FOX recesses) along STI edges. The divot at the edge of the STI is formed due to the wet dip of the pad oxide and/or sacrificial oxide by a hydrofluoric acid (HF) solution.
FIG. 1b is an overhead view of the 6T SRAM cell 100 of FIG. 1a, showing transistor gate stacks 102 crossing over divots 104 formed along the boundary 106 between active areas 108 and shallow trench isolation (STI) regions 110.
FIG. 1c is a cross-sectional view of the N2 transistor in the 6T SRAM cell 100 corresponding to the reference line X in FIG. 1b. FIG. 1c shows the gate dielectric 112 and gate electrode 114 deposited with a conformity greater than about 75%. If we do not use the word conformably deposited over divots 104. STI corners 116 in the active region 108 of the N2 transistor experience undesired current leakage. Because the gate dielectric 112 does not completely fill the divots 104, the divots 104 also comprise a portion of the gate electrode 114. The undesired extension of the gate dielectric 112 and gate electrode 114 along the sidewalls of the STI corners 116 may be a source of current leakage. Particularly, the non-planar shape of the gate dielectric 112 and gate electrode 114 at the STI corners 116 produces a concentrated electromagnetic field, thus causing STI corner current leakage. Additionally, the gate dielectric 112 experiences material stress over steps 118 in the divots 104, which may have an undesired effect on transistor power consumption.